Matthew H. Lee
625 Coyote Road
San Jose, California 95111
Home: (408) 629-8538
fastback66@yahoo.com
matthew.h.lee@lmco.com
Objective:
-
Seeking an electrical engineering position in hardware (ASIC) design or
development.
Technical Experience:
Dec, 1998-present:
-
Electrical Design Engineer,
-
Lockheed Martin Corporation Sunnyvale,
CA.
-
Fleet Ballistic Missiles Programs
-
FBM Systems Engineering, Electrical Design Group
Provide technical counsel to management, engineering staff, and buyers.
Project Management and Project Proposal
Sustaining Engineering (system upgrades, design verification, and sustaining
existing products)
April, 1996-March, 1998:
Electrical Engineer,
Lam Research Corporation Fremont,
CA
Systems/Automation, Hardware Product Development
Platform Engineering Department, Electrical Engineering Group
Developed AC/DC Power Distribution for Remote Power Module for Alliance
Cluster Tool Systems.
Developed System Interconnects for the Generic Frame Standalone Systems.
Developed and designed Power Distribution Cables for the Generic Frame
LVD Project.
Generated engineering and manufacturing requirements for both Dielectric
and Conductor Etch Product Line for the development of LVD, S2-93, UL/CSA,
and LVD/CE-97 compliant Subsystems and Components.
Jan. 1995-April, 1996:
Systems Engineer,
Varian Associates Palo Alto,
CA
Semiconductor Equipment Business,
Thin Film Systems MB2 Product Line/Advanced PVD Process Module
Maintained, repaired, and calibrated sputtering equipment.
Oversaw final test for the MB2 systems, recipe qualification, customer
acceptance of systems.
Troubleshot both electromechanical and motion control systems down to the
component level.
Performed general manufacturing engineering functions including resolution
of technical problems that would result in missing the production plan.
Maintained the accuracy of production documentation and data (B.O.M.).
Disposition of non-conforming material and initiate changes in the supplier
processes.
Outsourced of parts to vendor to achieve cost reduction.
Developed manufacturing specifications/procedures/processes/ECO.
Became the primary test floor contact for software problems.
June-Sept., 1994:
S.E.E.D. Internship,
Hewlett-Packard Company Boise,
ID
Advanced LaserJet
Operation, Toner Cartridge Engineering
Understanding Electrophotography, especially the interaction of charge/mass
ratio and their affects on toner cartridge performance.
Developed two methods of charge to mass (Q/m) measurement of toner, the
Faraday Cage Method and the E-Spart Analyzer Method.
Designed and built test fixtures for the Q/m method.
Education:
-
Santa Clara University, Santa Clara,
CA
-
Master of Science degree in Engineering Management
-
Major: Microelectronics and VLSI Design
-
Minor: Management and Leadership
-
Expected Graduation: June, 2000
-
University of California, Davis,
Davis, CA
-
Bachelor of Science degree in Mechanical
Engineering
-
Major: Mechatronics
-
Minor: Mathematics
-
Date of Graduation: December, 1994
Graduate Course Work:
Fundamentals of Semiconductor Physics (ELEN 261)
Integrated Circuit Fabrication Processes I and II (ELEN 274-275)
Integrated Circuit Design (ELEN 266)
VLSI Fabrication Technology I and II (ELEN 385-386)
Advanced Logic Design (ELEN 500)
Logic Design Using HDL (ELEN 603)
VLSI Design (ELEN 387)
Special Skills:
-
UNIX HP & SUN workstations / Windows NT workstations:
-
Electrical Design Software:
Mentor Graphics Logic & IC Design
Tools,
Cadence Verilog
XL Simulator.
Synopsys Design & Synthesis
tools.
Synplicity Design & Synthesis
tools.
Xilinx, Actel
FPGA tools.
Spice Circuit Simulation.
Mechanical Design Software:
AutoCad V12
SDRC-Ideas